Correlating Process Corners and Temperature in Deep Nano-scale CMOS
نویسنده
چکیده
Simulating variations pre-Si can be very time consuming. Running enough Monte Carlo simulations at the five process corners takes a non-trivial amount of time, particularly for larger designs. This paper describes a method for decreasing time for simulating process variations by reducing the number of required simulations. Through noise-analysis and Monte Carlo simulations conducted in commercial 28nm Fully Depleted Silicon On Insulator (FDSOI), we demonstrate that this method results in a reduction as large as one half in simulation time, depending on the size and type of circuit. Keywords—process compensation; process corners; manufacturing process variability; temperature compensation; subthreshold; 28 nm FDSOI; nano-scale CMOS
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تاریخ انتشار 2015